The present invention relates to a digital signal communication system employing multi-phase or multi-phase multi-amplitude modulation. More particularly it relates to a digital signal communication system of the modulation level of 2.sup.n (n.gtoreq.3) which includes differential logic circuits on the transmission and the receiver sides respectively.
As disclosed in "Differential Encoding for Multiple Amplitude and Phase Shaft Keying Systems" (W. J. Weber), IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-26, No. 3, pp. 385-391, March 1978, PSK (Phase Shift Keying) modulation, QAM (Quadrature Amplitude Modulation), and the likes have been widely used in digital signal communication systems. In these systems, however, since there may arise phase ambiguities in the carrier waves regenerated at a receiver, a differential logic circuit is generally used in order to eliminate such phase ambiguities.
In the digital radio communication systems, on the other hand, a parity check system is used to monitor the channel quality by the use of an odd or even parity bit for one monitoring section of transmission signals. As to such check systems, reference should be made to; K. Nakagawa et al "W-4DG Code Converters", Reviews of the Electrical Communication Laboratories, NTT, Japan, Volume 23, Nos. 7-8, July-August, 1975, pp. 799-817.
The conventional systems employing the differential logic circuits, however, are detrimental in that one bit error in the transmission path would cause two bit errors in the received and decoded signals. Such an error would incapacitate the parity check, or greatly deteriorate the error rate. U.S. Pat. No. 4,182,988 discloses a parity check system, which enables parity checking even in such a system by counting alternate bits. This U.S. patent and the subject invention are assigned to the same assignee. The patented system is still incapable of checking all of the bits and of using the conventional monitoring circuits.